at89c51單片機外文翻譯

1、<p>　　AT89C51的介紹</p><p>　?。ㄔ某鎏帲篽ttp：//yang63.go.nease.net/resource/mcu.htm）</p><p><b>　　描述</b></p><p>　　AT89C51是一個低電壓，高性能CMOS8位單片機帶有4K字節的可反復擦寫的程序存儲器（PENROM）。和128字節

2、的存取數據存儲器（RAM），這種器件采用ATMEL公司的高密度、不容易丟失存儲技術生產，并且能夠與MCS-51系列的單片機兼容。片內含有8位中央處理器和閃爍存儲單元，有較強的功能的AT89C51單片機能夠被應用到控制領域中。</p><p><b>　　功能特性</b></p><p>　　AT89C51提供以下的功能標準：4K字節閃爍存儲器，128字節隨機存取數據存

3、儲器，32個I/O口，2個16位定時/計數器，1個5向量兩級中斷結構，1個串行通信口，片內震蕩器和時鐘電路。另外，AT89C51還可以進行0HZ的靜態邏輯操作，并支持兩種軟件的節電模式。閑散方式停止中央處理器的工作，能夠允許隨機存取數據存儲器、定時/計數器、串行通信口及中斷系統繼續工作。掉電方式保存隨機存取數據存儲器中的內容，但震蕩器停止工作并禁止其它所有部件的工作直到下一個復位。</p><p><b&g

4、t;　　引腳描述</b></p><p>　　VCC：電源電壓 </p><p><b>　　GND：地</b></p><p><b>　　P0口：</b></p><p>　　P0口是一組8位漏極開路雙向I/O口，即地址/數據總線復用口。作為輸出口時，每一個管腳都能夠驅動8個T

5、TL電路。當“1”被寫入P0口時，每個管腳都能夠作為高阻抗輸入端。P0口還能夠在訪問外部數據存儲器或程序存儲器時，轉換地址和數據總線復用，并在這時激活內部的上拉電阻。P0口在閃爍編程時，P0口接收指令，在程序校驗時，輸出指令，需要接電阻。</p><p><b>　　P1口：</b></p><p>　　P1口一個帶內部上拉電阻的8位雙向I/O口，P1的輸出緩沖級可驅

6、動4個TTL電路。對端口寫“1”，通過內部的電阻把端口拉到高電平，此時可作為輸入口。因為內部有電阻，某個引腳被外部信號拉低時輸出一個電流。閃爍編程時和程序校驗時，P1口接收低8位地址。</p><p><b>　　P2口：</b></p><p>　　P2口是一個內部帶有上拉電阻的8位雙向I/O口，P2的輸出緩沖級可驅動4個TTL電路。對端口寫“1”，通過內部的電阻把

7、端口拉到高電平，此時，可作為輸入口。因為內部有電阻，某個引腳被外部信號拉低時會輸出一個電流。在訪問外部程序存儲器或16位地址的外部數據存儲器時，P2口送出高8位地址數據。在訪問8位地址的外部數據存儲器時，P2口線上的內容在整個運行期間不變。閃爍編程或校驗時，P2口接收高位地址和其它控制信號。</p><p><b>　　P3口：</b></p><p>　　P3口是一

8、組帶有內部電阻的8位雙向I/O口，P3口輸出緩沖故可驅動4個TTL電路。對P3口寫如“1”時，它們被內部電阻拉到高電平并可作為輸入端時，被外部拉低的P3口將用電阻輸出電流。</p><p>　　P3口除了作為一般的I/O口外，更重要的用途是它的第二功能，如下表所示：</p><p>　　P3口還接收一些用于閃爍存儲器編程和程序校驗的控制信號。</p><p><

9、;b>　　RST：</b></p><p>　　復位輸入。當震蕩器工作時，RET引腳出現兩個機器周期以上的高電平將使單片機復位。</p><p><b>　　ALE/：</b></p><p>　　當訪問外部程序存儲器或數據存儲器時，ALE輸出脈沖用于鎖存地址的低8位字節。即使不訪問外部存儲器，ALE以時鐘震蕩頻率的1/16輸

10、出固定的正脈沖信號，因此它可對輸出時鐘或用于定時目的。要注意的是：每當訪問外部數據存儲器時將跳過一個ALE脈沖時，閃爍存儲器編程時，這個引腳還用于輸入編程脈沖。如果必要，可對特殊寄存器區中的8EH單元的D0位置禁止ALE操作。這個位置后只有一條MOVX和MOVC指令ALE才會被應用。此外，這個引腳會微弱拉高，單片機執行外部程序時，應設置ALE無效。</p><p><b>　　PSEN：</b&g

11、t;</p><p>　　程序儲存允許輸出是外部程序存儲器的讀選通信號，當AT89C51由外部程序存儲器讀取指令時，每個機器周期兩次PSEN 有效，即輸出兩個脈沖。在此期間，當訪問外部數據存儲器時，這兩次有效的PSEN 信號不出現。</p><p><b>　　EA/VPP：</b></p><p>　　外部訪問允許。欲使中央處理器僅訪問外部程

12、序存儲器，EA端必須保持低電平。需要注意的是：如果加密位LBI被編程，復位時內部會鎖存EA端狀態。如EA端為高電平，CPU則執行內部程序存儲器中的指令。閃爍存儲器編程時，該引腳加上+12V的編程允許電壓VPP，當然這必須是該器件是使用12V編程電壓VPP。</p><p>　　XTAL1：震蕩器反相放大器及內部時鐘發生器的輸入端。</p><p>　　XTAL2：震蕩器反相放大器的輸出端。

13、</p><p><b>　　時鐘震蕩器</b></p><p>　　AT89C51中有一個用于構成內部震蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入端和輸出端。這個放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構成自然震蕩器。 外接石英晶體及電容C1，C2接在放大器的反饋回路中構成并聯震蕩電路。對外接電容C1，C2雖然沒有十分嚴格的要求

14、，但電容容量的大小會輕微影響震蕩頻率的高低、震蕩器工作的穩定性、起振的難易程序及溫度穩定性。如果使用石英晶體，我們推薦電容使用30PF±10PF，而如果使用陶瓷振蕩器建議選擇40PF±10PF。用戶也可以采用外部時鐘。采用外部時鐘的電路如圖示。這種情況下，外部時鐘脈沖接到XTAL1端，即內部時鐘發生器的輸入端，XTAL2則懸空。由于外部時鐘信號是通過一個2分頻觸發器后作為內部時鐘信號的，所以對外部時鐘信號的占空比沒有

15、特殊要求，但最小高電平持續時間和最大的低電平持續時間應符合產品技術條件的要求。</p><p>　　內部振蕩電路 外部振蕩電路</p><p><b>　　閑散節電模式</b></p><p>　　AT89C51有兩種可用軟件編程的省電模式，它們是閑散模式和掉電工作模式。這兩種方

16、式是控制專用寄存器PCON中的PD和IDL位來實現的。PD是掉電模式，當PD=1時，激活掉電工作模式，單片機進入掉電工作狀態。IDL是閑散等待方式，當IDL=1，激活閑散工作狀態，單片機進入睡眠狀態。如需要同時進入兩種工作模式，即PD和IDL同時為1，則先激活掉電模式。在閑散工作模式狀態，中央處理器CPU保持睡眠狀態，而所有片內的外設仍保持激活狀態，這種方式由軟件產生。此時，片內隨機存取數據存儲器和所有特殊功能寄存器的內容保持不變。閑散

17、模式可由任何允許的中斷請求或硬件復位終止。終止閑散工作模式的方法有兩種，一是任何一條被允許中斷的事件被激活，IDL被硬件清除，即刻終止閑散工作模式。程序會首先影響中斷，進入中斷服務程序，執行完中斷服務程序，并緊隨RETI指令后，下一條要執行的指令就是使單片機進入閑散工作模式，那條指令后面的一條指令。二是通過硬件復位也可將閑散工作模式終止。需要注意的是：當由硬件復位來終止閑散工作模式時，中央處理器CPU通常是從激活空閑模式那條指令的下一條

18、開始繼續執行程序的，要完成內部復位操作</p><p><b>　　掉電模式</b></p><p>　　在掉電模式下，振蕩器停止工作，進入掉電模式的指令是最后一條被執行的指令，片內RAM和特殊功能寄存器的內容在中指掉電模式前被凍結。退出掉電模式的唯一方法是硬件復位，復位后將從新定義全部特殊功能寄存器但不改變RAM中的內容，在VCC恢復到正常工作電平前，復位應無效切必

19、須保持一定時間以使振蕩器從新啟動并穩定工作。</p><p>　　閑散和掉電模式外部引腳狀態。</p><p><b>　　程序存儲器的加密</b></p><p>　　AT89C51可使用對芯片上的三個加密位LB1，LB2，LB3進行編程（P）或不編程（U）得到如下表所示的功能：</p><p>　　當LB1被編程時，

20、在復位期間，EA端的電平被鎖存，如果單片機上電后一直沒有復位，鎖存起來的初始值是一個不確定數，這個不確定數會一直保存到真正復位位置。為了使單片機正常工作，被鎖存的EA電平與這個引腳當前輯電平一致。機密位只能通過整片擦除的方法清除。</p><p>　　Description</p><p>　　The AT89C51 is a low-power, high-performance CMO

21、S 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-sta

22、ndard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a mon

23、olithic chip</p><p>　　Function characteristic</p><p>　　The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five

24、vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two sof

25、tware selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to </p><p>　　Pin Description</p><p>　　VCC：Supply voltage

26、.</p><p>　　GND：Ground.</p><p><b>　　Port 0：</b></p><p>　　Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. Whe

27、n 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mod

28、e P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are requ</p><p><b>　　Port 1</b></

29、p><p>　　Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups

30、 and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming a

31、nd verification.</p><p><b>　　Port 2</b></p><p>　　Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s ar

32、e written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal pullups.Port 2 emit

33、s the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In</p><p><b>　　Port 3</b></p><p>　　Po

34、rt 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as

35、inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:</p>

36、<p>　　Port 3 also receives some control signals for Flash programming and verification.</p><p><b>　　RST</b></p><p>　　Reset input. A high on this pin for two machine cycles whil

37、e the oscillator is running resets the device.</p><p><b>　　ALE/PROG</b></p><p>　　Address Latch Enable output pulse for latching the low byte of the address during accesses to externa

38、l memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking pu

39、rposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.</p><p>　　If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE

40、 is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.</p><p><b>　　

41、PSEN</b></p><p>　　Program Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except

42、that two PSEN activations are skipped during each access to external data memory.</p><p><b>　　EA/VPP</b></p><p>　　External Access Enable. EA must be strapped to GND in order to enabl

43、e the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for in

44、ternal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.</p><p><b>　　XTAL1</b></p><p>

45、;　　Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p><b>　　XTAL2</b></p><p>　　Output from the inverting oscillator amplifier.</p

46、><p>　　Oscillator Characteristics</p><p>　　XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Fig

47、ure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on

48、the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two fli</p><p>　　Figure 1. Oscillator Connections Figure 2. External Clock Dri

49、ve Configuration</p><p><b>　　Idle Mode</b></p><p>　　In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The co

50、ntent of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is ter

51、minated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset</p><p>　　Power-down Mode</p><p>　　In the po

52、wer-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is term

53、inated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be

54、held active long enough to allow the oscillator to </p><p>　　Program Memory Lock Bits</p><p>　　On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obta

55、in the additional features listed in the table below.</p><p>　　When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, t

56、he latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to func